Browse Prior Art Database

Variable Symmetry Fixed Frequency Oscillator Control Circuit

IP.com Disclosure Number: IPCOM000085675D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Calvo, R: AUTHOR [+2]

Abstract

This control circuit for a push-pull inverter operates to keep the currents in the two sides of the inverter 10 equal, so that walking of the core 12 of a transformer driven by the inverter is avoided. The circuit utilizes sample and hold voltage inputs derived at 14, 16 from the currents flowing in two sides of the inverter 10, operates to adjust the symmetry of the inverter operation to keep those currents balanced.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 65% of the total text.

Page 1 of 2

Variable Symmetry Fixed Frequency Oscillator Control Circuit

This control circuit for a push-pull inverter operates to keep the currents in the two sides of the inverter 10 equal, so that walking of the core 12 of a transformer driven by the inverter is avoided. The circuit utilizes sample and hold voltage inputs derived at 14, 16 from the currents flowing in two sides of the inverter 10, operates to adjust the symmetry of the inverter operation to keep those currents balanced.

The circuit generates two currents, i(x) and i(y), one of which is proportional to the difference between the two sample and hold voltages and the other is proportional to the negative of the difference between those two voltages with each having a bias term and with the common-mode value of the voltage being cancelled out.

As shown in the figure the control utilizes a symmetrical arrangement, each side of which includes a transistor Q1, Q10 connected as a diode, in parallel with the base-emitter junction of another transistor Q2, Q9, whereby the currents through the two devices are the same. A current i(a) proportional to one sample and hold voltage V(A) is sent through transistor Q1 and a current i(B) proportional to the other sample voltage V(B) is fed to junction 18, to which the collector of transistor Q2 and the base lead of a third transistor Q3 are connected. Thus, the base of transistor Q3 receives current which is the difference of the two sample currents. An additional stage Q4...