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High Input Impedance TTL Receiver Circuit

IP.com Disclosure Number: IPCOM000085686D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Sechler, RF: AUTHOR

Abstract

A TTL (transistor, transistor logic) receiver circuit is provided which has high-input impedance comparable to a current switch circuit with no additional circuit delay.

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High Input Impedance TTL Receiver Circuit

A TTL (transistor, transistor logic) receiver circuit is provided which has high- input impedance comparable to a current switch circuit with no additional circuit delay.

The standard TTL receiver circuit, as shown in Fig. 1a, is hindered by its relatively low-input impedance while the current switch receiver circuit, as shown in Fig. 1b, provides a high-input impedance at a substantial delay penalty, due to the lack of a TTL compatible logic operation. There are many applications where a high-input impedance receiver is necessary, such as long-line communications.

The use of a current source (collector of transistor Q1, shown in Fig. 2a) in place of the receive resistor Rpd (Fig. 1a) offers two advantages in power dissipation. Such a current source can be used as the TTL source of off-current for the implementation of both Figs. 2a and b. A power savings is realized over Fig. 1a, because the current during a positive signal is no greater than that during a negative signal. For the current switch receiver case, Fig. 1b, a power savings is realized due to the lack of a requirement to double up on receive resistors, in order to provide the required off-current. It is estimated that an overall savings of 2O to 25% of receive power can be obtained. This would definitely be worthwhile in an air-cooled environment.

No substantial change in input impedance is anticipated for the implementation of Fig. 2a. The higher resistance of the collector receiver might be expected to compensate for the higher capacitance of the collector, with no change in the low impedance parallel TTL circuit.

Another advantage of the circuitry of Figs. 2a and 2b is that the same circuit could be used for each case. In summary, the receive circuitry of Figs. 2a and 2b offers power and layout advantages over the receive circuitry of Figs. 1a and 1b, but shares their disadvantages, namely low-input impedance at high speed, and a delay penal...