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Skew Meter

IP.com Disclosure Number: IPCOM000085693D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Jenkins, MO: AUTHOR

Abstract

This skew meter measures the jitter in the subnanosecond range on an edge-by-edge basis, by determining the maximum time error (skew) between a reference and a waveform under test for a large number of sampled edges.

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Skew Meter

This skew meter measures the jitter in the subnanosecond range on an edge-by-edge basis, by determining the maximum time error (skew) between a reference and a waveform under test for a large number of sampled edges.

Referring to the block diagram, the input IN1 is the clock pulse whose timing is to be determined with respect to a reference input IN2. The input sampling circuit 10 selects every 128 pair of positive-going edges. The timing of both inputs IN1 and IN2 is extracted in a respective pair of latches. The 128 sampling selections are obtained by a divider arrangement which essentially divides by 128.

The skew amplifier 12 increases the skew between the input edges. The falling edges at IN1 and IN2 begin the discharge of capacitors within the skew amplifier 12. When these capacitor voltages fall below a threshold value, a negative edge occurs at the output of the amplifier 12. The skew amplifier multiplies input skews less than about 500 picoseconds by a factor of approximately 100.

The resulting skew (in the range of 50 nanoseconds or less) is converted to a pulse width via logic gates within the phase comparator 14. The output from the phase comparator 14 is on two lines, the output depending on whether the phase difference or skew is lagging or leading. These pulse widths are converted to voltages in the pulse width detector 16, wherein the maximum voltage is sampled at approximately 1 second intervals to become the "peak skew output".

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