Browse Prior Art Database

High Speed Binary and Decimal Multiply by Array Assist

IP.com Disclosure Number: IPCOM000085694D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Singh, S: AUTHOR [+2]

Abstract

Described is a means to reduce the amount of logic in a high-speed binary, decimal, or a combined binary and decimal multiplier by prestoring a limited number of multiples of the multiplicand in an array (arrays), and using a group (groups) of multiplier bits to select a stored multiple (multiples) in shifted or unshifted, and/or complemented or uncomplemented form.

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High Speed Binary and Decimal Multiply by Array Assist

Described is a means to reduce the amount of logic in a high-speed binary, decimal, or a combined binary and decimal multiplier by prestoring a limited number of multiples of the multiplicand in an array (arrays), and using a group (groups) of multiplier bits to select a stored multiple (multiples) in shifted or unshifted, and/or complemented or uncomplemented form.

High-speed multiply methods are shown using two local working stores for storage of two decimal or hexadecimal digit multiples of the multiplicand. It is known that not all the multiples of a multiplicand are necessary. The multiplier digits 1A and 1B are decoded in parallel, and the decoder 2 outputs address the local working stores 3A and 3B for the proper multiple of the multiplicand.

The outputs 4A and 4B of the decoder control the true and complement gate mechanism of an adder apparatus 5 used for the iterative addition process involved in multiplication.

One dedicated piece of hardware for multiply will be a decoder, decoding for each of the two digits 5 bits of multiplier with an overlap of one bit every iteration (cycle). Since it is desirable that a minimum number of multiples of the multiplicand be stored to save preparatory cycles, simple gating mechanisms such as left 0, 1, 2 and 3 shift capability 6A and 6B at the outputs of local working stores 3A and 3B is required. This gating mechanism along with the true and complement gating to...