Browse Prior Art Database

Multiplier Decoder

IP.com Disclosure Number: IPCOM000085695D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Singh, S: AUTHOR

Abstract

The use of a series of carry-save adders to perform multiply and divide in high performance data processing systems is shown in U.S. Patents 3,508,038 and 3,515,344. Described is a modification to the multiplier decoding which reduces the number of iterations required to perform binary and hex-floating multiply operations.

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Multiplier Decoder

The use of a series of carry-save adders to perform multiply and divide in high performance data processing systems is shown in U.S. Patents 3,508,038 and 3,515,344. Described is a modification to the multiplier decoding which reduces the number of iterations required to perform binary and hex-floating multiply operations.

The figure depicts the series of carry-save adders essentially as shown in the above referenced patents. In the teaching of these patents, four multiples of a multiplicand (M1, M2, M3, M4) are generated on each of a plurality of iterations, in which multiplier bits are decoded 8 bits at a time with one bit overlap.

In the teaching of the patents, the outputs 1 and 2 from CSAD are normally looped around as inputs to CSAA and CSAB for combination with further multiples on following iterations. In the teachings of the patents, the first iteration assumes an additional low-order binary 0 for the multiplier.

In accordance with the present teaching, the first iteration assumes two low- order binary 0's for the purpose of generating a multiple M0 on input line 3. A gate 4 selectively applies multiple M0 or intermediate results on line 1. During the first cycle, the input on line 1 would be binary 0 and therefore can be utilized for applying multiple M0 to CSAB. Subsequent iterations in accordance with the above showing, would combine intermediate results on line 1 and 2 with the normal multiple generations M1-M4.

By assuming two low...