Browse Prior Art Database

Address Expansion Device

IP.com Disclosure Number: IPCOM000085701D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Glaser, TW: AUTHOR

Abstract

This device fills the need for a low-cost means of providing additional ROS (read-only store) page addresses on an existing machine to implement additional functions, without affecting the basic architecture of the machine and basically is the combining of a ROS module 20 with peripheral logic, such that the instruction placement on a portion of module 20 can control the active/inactive states of the same module.

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Address Expansion Device

This device fills the need for a low-cost means of providing additional ROS (read-only store) page addresses on an existing machine to implement additional functions, without affecting the basic architecture of the machine and basically is the combining of a ROS module 20 with peripheral logic, such that the instruction placement on a portion of module 20 can control the active/inactive states of the same module.

The device is particularly suitable for application to the IBM 3741 Data Entry Device by which data may be entered onto a magnetic disk from a keyboard. The original architecture of the 3741 machine provides 64 distinct ROS page addresses, with four of these pages allotted for features that can be added to the original machine. Also provided in the original machine, are 32 linkages from various points in the basic machine microcode to a continuous block of 32 instruction addresses contained on one of the pages allotted for such additional features.

There also exists means for dividing the basic ROS into "groups" such that several different ROS modules can contain the same physical page assignments. The selection of which of these modules is to be active can be controlled by the logic contained in other modules.

Two additional FET (field-effect transistor) modules are required to control this process. The device according to the present description solves this problem by allowing the same type of address duplication (thus allowing extension of the number of addressable instructions), but it uses a relatively inexpensive method of control.

Referring to the figure the device according to the present method used to accomplish this function consists of ROS module 20 containing control information and the logic for the features to be added and six TALL (transistor transistor logic) packages. ROS module 20 is held inactive until such time as an address within the 32 instruction linkage block 22 is decoded by the TTL logic provided by the illustrated device. When such an address is decoded, ROS module 20 is activated; and selected basic machine ROS modules 24 and 26 are deactivated. A TTL latch 28 is provided to latch the machine into this state when required, and is set and/or reset based upon...