Browse Prior Art Database

Accessing Storage Direct Areas

IP.com Disclosure Number: IPCOM000085709D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR

Abstract

Control storage in a computer system is provided with storage direct areas which are fixed storage areas for containing certain registers and work spaces. It is desirable to have a storage direct area for each block of storage. An available register which can be loaded via the instruction address register is used to select a block of storage containing the storage direct area.

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Accessing Storage Direct Areas

Control storage in a computer system is provided with storage direct areas which are fixed storage areas for containing certain registers and work spaces. It is desirable to have a storage direct area for each block of storage. An available register which can be loaded via the instruction address register is used to select a block of storage containing the storage direct area.

The storage direct areas are accessed by a Storage Direct instruction shown in Fig. 1; however, the block of storage containing the desired storage direct area is selected by the contents of an existing operand register. The contents of this operand register are gated to be concatenated with address bits from the Storage Direct instruction. Bits 0-3 of the Storage Direct instruction contain the OP code, bit 4 indicates whether a read or write operation takes place, bits 5-7 select the data source or destination, bit 8 is an 0P code modifier, and for this instruction is always zero, and bits 9 - 15 specify a location in one of the storage direct areas.

In Fig. 2 control storage 10 is represented as two blocks of 4K two-byte words. Each block has a storage direct area of 128 words. The particular block of storage is selected by appropriately loading the instruction address register (MAR) located in LSR's 100, Fig. 3, prior to fetching the Storage Direct instruction. The contents of MAR (16 bits) are loaded into X register HI and LO at TO time, see also Fig. 4, which is the first time step for fetching the Storage Direct instruction.

High-order bits 0-3 of X register HI and bits 4-7 f...