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Logic Packaging for Pattern Recognition Machines

IP.com Disclosure Number: IPCOM000085710D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Benson, GG: AUTHOR

Abstract

In a conventional type of optical character recognition (OCR) system, Fig. 1, the serial output 10 of a flying-spot scanner is transmitted through a number of multistage shift registers 11 to form a two-dimensional image of the scan field. Various stages of registers 11 are connected to Boolean logic 12 to determine the presence of certain combinations in the scanned pattern.

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Logic Packaging for Pattern Recognition Machines

In a conventional type of optical character recognition (OCR) system, Fig. 1, the serial output 10 of a flying-spot scanner is transmitted through a number of multistage shift registers 11 to form a two-dimensional image of the scan field. Various stages of registers 11 are connected to Boolean logic 12 to determine the presence of certain combinations in the scanned pattern.

Outputs 13 represent either the presence of particular characters, or the presence of features which are used by further logic, not shown, to detect entire characters. This type of system may be adapted to parallel-channel scanners by feeding the channels into separate registers 11 in parallel, as at 10' and 10".

As integrated Circuit (IC) logic becomes ever more dense, it is desirable to place logic modules 12 in a small number of packages. But, while the logic itself can be integrated easily, the number of input and output pins becomes prohibitive. Thus, the total number of packages cannot be significantly reduced.

Fig. 2 shows a recognition system which greatly reduces inter-package connections. Multichannel scanner 20 includes shift registers for shifting video data onto bus 21 serially by row and parallel by column. Bus 21 is coupled to a small number of IC packages 30, 40 which contain both shift registers and random-logic elements. Registers 31, 41 can be truncated after the last stage in each column which is required for the logic 32,...