Browse Prior Art Database

Cache Memory With Prefetching of Data by Priority

IP.com Disclosure Number: IPCOM000085760D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Bennett, BT: AUTHOR [+2]

Abstract

The data management scheme illustrated in the drawings improves the miss ratio in a cache memory organization by prefetching, during otherwise idle memory cycles, lines adjacent to a requested line for which a page fault has occurred.

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Cache Memory With Prefetching of Data by Priority

The data management scheme illustrated in the drawings improves the miss ratio in a cache memory organization by prefetching, during otherwise idle memory cycles, lines adjacent to a requested line for which a page fault has occurred.

The candidates for prefetching are stored in a candidate memory which is continuously updated upon each page fault.

With reference to the drawings, Fig. 1 shows the cache memories C , C , and C each of which stores a corresponding line number from a page, if it is to be stored. The Units A1, A2 and A3 are associative memories that keep track of the page contents of the correspondingly numbered cache memories and yield the address thereof upon request from the CPU or, in the absence of a line in the cache, produce a page fault signal to fetch the requested line from main memory, enter it into the appropriate cache C1, C2 or C3 and update the associative memory to enter the new line ID and expunge the bumped line ID. The least recently used (LRU) rules govern the replacement of data in the cache memory.

The system may prepare itself for the prefetching whenever a page fault occurs, or whenever a reference to a line occurs, even though it may be a resident in the cache. Prefetching is effected, however, only during idle memory cycles. P1, P2 and P3 in Fig. 1 are priority prefetching devices as shown in Fig. 3, respectively associated with memories M1, M2 and M3.

When a page fault occurs and the sought page line is fetched from one of the memories M1, M2, M3, etc....