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Pseudo Bucket Brigade Operation in Bipolar Technology

IP.com Disclosure Number: IPCOM000085777D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

Described is a bipolar embodiment of a bucket brigade shift register in which the high-signal loss normally found in bipolar bucket brigades is avoided, thus providing faster operation than a field-effect transistor (FET) bucket brigade shift register and longer shift registers.

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Pseudo Bucket Brigade Operation in Bipolar Technology

Described is a bipolar embodiment of a bucket brigade shift register in which the high-signal loss normally found in bipolar bucket brigades is avoided, thus providing faster operation than a field-effect transistor (FET) bucket brigade shift register and longer shift registers.

The storage and signal processing techniques of charge-transfer devices such as bucket brigade shift registers have heretofore been largely limited to FET devices. However, a simple duality to the FET bucket brigade circuit exits and bipolar devices are substituted for the FET devices. Such simple substitution, however, causes the circuit to suffer exorbitant signal loss through the base and, therefore, is impractical.

The circuit shown in the figure, however, avoids all of the difficulties known to the prior art and realizes the high speed of bipolar technology along with the high-signal fidelity of a field-effect structure.

The figure shows two identical stages, stage 1 and stage 2. Stage 1 comprises a bipolar transistor 10 having its emitter coupled to a voltage at node 11, its base coupled to a current source 12 and to the source 13 of junction (J) FET whose source 15 is coupled to ground. The gate 16 of the JFET is coupled to a node 14 which is also connected to one side of a capacitor 17 whose other side is coupled to the collector of transistor 10 and to ground through a load resistor 18, which also couples the collector of transistor 10 to ground. Also coupled to the node 14 of the JFET is a diode 19 coupled through a signal resistor 20 to the node 14a of stage 2.

Stage 2 is identical to stage 1 and for convenience the same numerals are used with the suffix "a" appended thereto. When an input signal is received at node 14 in stage 1, the JFET measures the input signal and permits the transistor 10 to remain on and draw current through resistor 18 until...