Browse Prior Art Database

Delay Pulse Driver

IP.com Disclosure Number: IPCOM000085778D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Rossi, FR: AUTHOR [+2]

Abstract

This field-effect transistor (FET) pulse driver circuit provides a delayed output pulse having a rise time independent of the rise time of the input signal. The circuit is useful in timing pulse generation circuits in which sequential clock pulses are derived from serially connected delay/ driver circuits.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 2

Delay Pulse Driver

This field-effect transistor (FET) pulse driver circuit provides a delayed output pulse having a rise time independent of the rise time of the input signal. The circuit is useful in timing pulse generation circuits in which sequential clock pulses are derived from serially connected delay/ driver circuits.

Typical FET delay/driver circuits are sensitive to input pulse rise time and, if the output of any preceding driver is slower than expected, the entire timing chain could be seriously affected. This circuit avoids that problem, has low-input capacitance and uses little power. Each driver stage may be easily tuned for desired power-performance requirements.

During a restore portion of a cycle, restore pulse R through transistors 5 and 21 precharges nodes B and I, respectively, to V-VT and transistors 13, 19 and 10, respectively, connect nodes A, H and Vout to ground. Node F rises to V through resistor R as node G and C are held to ground by input pulse Vin. After pulse R falls, Vin may rise causing nodes B and I to be bootstrapped allowing nodes G and C to rise. Transistor T15 turns on pulling node F toward ground while the gate of transistor T1 is being precharged.

Vin also turns on transistor T18 causing node H to attempt to charge node capacitance CH. Transistor T23, having its gate connected to node G, diverts some of the charging current to ground allowing node H to rise at a rate dependent on the sizes of T18, T23 and capacitor CH.

When...