Browse Prior Art Database

Memory Address Decode Circuit

IP.com Disclosure Number: IPCOM000085779D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Huffman, DR: AUTHOR [+3]

Abstract

This field-effect transistor (FET) address decode circuit allows a reduction in the size of devices needed to drive address lines in a memory array, thus reducing the decode pitch and enabling design of higher density memory arrays.

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Memory Address Decode Circuit

This field-effect transistor (FET) address decode circuit allows a reduction in the size of devices needed to drive address lines in a memory array, thus reducing the decode pitch and enabling design of higher density memory arrays.

In a typical address decode circuit a precharge clock pulse having an amplitude of V is applied to the gate of transistor T3 causing node B to be precharged to V-Vt. In order to obtain desired performance, device T5 and bootstrap capacitor CB must be made large. The use of large drivers (T5) causes the decode pitch to control the maximum density of the memory array. This circuit provides a reduction in the required size of device T5 and capacitor CB by providing a bootstrapped precharge clock pulse, from buffer driver 10, of greater than supply potential V which allows transistor T3 to precharge node B to supply potential V. Node A will be charged to IV-VT.

When node C is discharged nodes A and B remain charged. If the decoder is not to be selected, at least one of the n input SARs will rise discharging nodes A and B. When word line drive pulse Vw rises, the word line remains at zero volts because the gate of device T5 is at ground.

If the decoder is to be selected, all SARs remain low and nodes A and B remain charged. When Vw rises to V, it is coupled to node B by bootstrap capacitor CB causing node B to be bootstrapped sufficiently above V to provide V on the word line.

Because each address line (word l...