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Multiprocessor Input Output Interrupt Mechanism

IP.com Disclosure Number: IPCOM000085791D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Drimak, EG: AUTHOR

Abstract

A mechanism is provided for distributing input/output (I/O) interrupts across two digital data processors and for providing high-speed message buses between the two processors.

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Multiprocessor Input Output Interrupt Mechanism

A mechanism is provided for distributing input/output (I/O) interrupts across two digital data processors and for providing high-speed message buses between the two processors.

Fig. 1 shows a two-way multiprocessing system having two main processors A and B, two input/output (I/O) controllers A and B and twelve I/O channels. Storage for the system is not shown but appropriate data paths to and from storage exist for each processor and I/O controller. The I/O interrupt mechanism provides two modes of system operation, namely, a segregated mode and an integrated mode.

In the segregated mode, I/O interrupts from channels 0-5 are handled only by processor A and I/O interrupts from channels 6-11 are handled only by processor
B. The integrated mode, on the other hand, provides a priority level interrupt structure which allows device interrupts from all of channels 0-11 to be assigned to different interrupt priority levels, and distributed to both processors independently of the physical channel connections of the devices.

Mask/message buses A and B are a key feature of the mechanism and provide a dual function in the system. One function is an interrupt mask function and is used to communicate to one processor the current interrupt handling capabilities of the other processor. This is done by an interrupt mask which is transmitted on the mask/message bus. The other function of the mask/message buses A and B is to provide high-speed message buses between the two processors for synchronization purposes such as, for example, to prevent concurrent execution of conflicting instructions. Each of the mask/message buses A and B consists of sixteen lines plus one control line, the latter being shown separately for sake of explanation.

Fig. 2 shows a typical timing sequence for the case where a message is sent from processor A to processor B. An uplevel on the control line A signals the processor B that a message is being sent. Processor A then places a message on the mask/message bus A and waits for a response. The message causes a special interrupt in processor B. Processor B then reads the message and responds on its mask/message bus B. This procedure is reversed when processor B is sending a message to processor A.

When not sending or responding to messages, mask/message buses A and B are used to send interrupt masks to the other processor. The mask on bus A, for example, tells processor B which...