Browse Prior Art Database

Hardware Assist for Microcode Execution of Storage to Storage Move Instructions

IP.com Disclosure Number: IPCOM000085798D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 44K

Publishing Venue

IBM

Related People

Dvorak, TJ: AUTHOR [+3]

Abstract

A hardware mechanism is provided for altering the control store microword address during execution of a storage-to-storage move instruction to enable faster execution of such instruction.

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Hardware Assist for Microcode Execution of Storage to Storage Move Instructions

A hardware mechanism is provided for altering the control store microword address during execution of a storage-to-storage move instruction to enable faster execution of such instruction.

In current microprogrammed digital computers and data processors, storage- to-storage move type machine instructions are boundary aligned and executed by the microcode until completion. This requires the following microcode routines: (1) A boundary checking routine for operand No. 1; (2) A boundary alignment routine for operand No. 1; (3) A storage-to-storage data transfer routine; and (4) A checking routine to determine if an exit is required or if a branch back to the data transfer routine is in order.

The hardware assist mechanism described herein enables a storage-to- storage move instruction to be executed with only the following microcode routines being required: (A) A boundary alignment routine for operand No. 1; and (B) A storage-to-storage data transfer routine.

In other words, the mechanism described herein uses hardware to replace the item (1) and item (4) microcode routines used in the case of existing data processors.

Fig. 1 shows the format for the storage-to-storage move type machine instructions being considered herein. The purpose of the move instruction is to take data in storage starting at the storage address designated by the operand No. 2 address, and to move it or restore it in storage locations starting with the storage address designated by the operand No. 1 address. The length field in the instruction specifies the number of bytes of data to be moved. This length is variable and can range from 1 to 256 bytes. The specified length of data is to be moved from the operand No. 2 starting location to the operand No. 1 starting location in the data storage unit of the data processor.

Fig. 2 shows the hardware for performing the boundary checking routine for operand No. 1. Fig. 3 is a high-level flow chart for the microcode used to perform the boundary alignment routine for operand No. 1 and the storage-to- storage data transfer routine. Fig. 4 (and part of Fig. 2) shows the hardware used to replace the branch back checking routine.

As indicated in Fig. 3, there are four different entry points, designated 10-13, for entering into the microcode for this instruction. If the value in the instruction length field is less than six, entry is made at point 10. If, on the other hand, the length value is equal to or greater than six, then entry is made at the appropriate one of points 11-13. The appropriate one of these three entry points 11-13 is determined by the AND circuits 14, 15 and 16 shown in Fig. 2.

Thus, for example, if the operand No. 1 starting address falls on a fullword (F/W) boundary, then AND circuit 14 forces an entry into the microcode at the F/W entry point 13. If it falls on a halfword (H/W) boundary, then AND circuit 15 forces entry at p...