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Input Output Subchannel Request Queuing Mechanism

IP.com Disclosure Number: IPCOM000085804D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Boggs, JK: AUTHOR [+3]

Abstract

A mechanism is described for implementing subchannel request queuing for the input/output (I/O) system associated with a digital data processor.

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Input Output Subchannel Request Queuing Mechanism

A mechanism is described for implementing subchannel request queuing for the input/output (I/O) system associated with a digital data processor.

The drawing shows a typical setup for an I/O system for a data processor. It includes a pair of I/O channels 11 and 12 for providing communication between the processor unit 10 and the different groups of I/O devices 13. In this environment, a subchannel is defined as being the channel facilities required for sustaining a single I/O operation. It is assumed herein that each channel has multiple subchannels for supporting its I/O devices 13.

The mechanism described herein enables "one deep" queuing of I/O requests for each of the different subchannels. Thus, if the channel is busy, the I/O request for a particular subchannel therein will be queued, provided such subchannel does not already have a pending queued I/O request. This mechanism operates in a strictly first-in first-out (FIFO) manner.

The implementation of this mechanism requires that certain kinds of control blocks or dedicated storage areas be available in the main storage unit 14. Some of these control blocks are made available only to the processor hardware. These are: (a) Subchannel control word (SCW) block. This storage area stores subchannel control words which represent the status of the various subchannels.
(b) Channel control word (CCW) block. This storage area stores the status of the channel and is the queue header of sub-channel control words representing queued work for the channel. (c) Interrupt queue (IQ) block. This storage area holds the queue header of subchannel control words representing completed work to be reported to the processor unit 10. (d) Interface directory (ID) block. This is a storage area which is indexed using the I/O interface address. Each defined interface address contains a corresponding subchannel control word address through which the I/O work is performed.

Other of these control block storage areas are made visible to the software. These include:. (a) I/O request (IOR) block. This storage area stores the interface and channel address, the address of an appropriate set of I/O commands and a protection key value under which dat...