Browse Prior Art Database

Asynchronous Performance of I/O Halt Device Instructions

IP.com Disclosure Number: IPCOM000085806D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Boggs, JK: AUTHOR

Abstract

A mechanism is provided for enabling improved performance of HALT DEVICE (HDV) instructions for the case of data processors having one or more very high-speed input/output (I/O) devices connected thereto. The mechanism enables HALT DEVICE operations to be performed in either a synchronous manner or an asynchronous manner relative to the central processor unit (CPU), depending upon the type of I/O device involved in the operation. In particular, synchronous operation is provided for low-speed devices on a byte multiplexer channel and asynchronous operation is provided for high-speed devices on a channel which is not a byte multiplexer channel.

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Asynchronous Performance of I/O Halt Device Instructions

A mechanism is provided for enabling improved performance of HALT DEVICE (HDV) instructions for the case of data processors having one or more very high-speed input/output (I/O) devices connected thereto. The mechanism enables HALT DEVICE operations to be performed in either a synchronous manner or an asynchronous manner relative to the central processor unit (CPU), depending upon the type of I/O device involved in the operation. In particular, synchronous operation is provided for low-speed devices on a byte multiplexer channel and asynchronous operation is provided for high-speed devices on a channel which is not a byte multiplexer channel.

In the performance of a HALT DEVICE instruction, the processor unit notifies the channel that the device is to be stopped. In the case of synchronous operation, the processor unit sits and waits until it receives back from the channel a signal telling it that the device has been halted. This waiting can take a significant amount of time in the case of a high-speed device because it takes time to get such a device stopped.

The mechanism described herein eliminates this tying up of the processor unit by automatically providing asynchronous operation for the case of a high- speed I/O device. In particular, as soon as the channel receives the request to stop, it immediately sends a signal back to the processor unit acknowledging receipt of the request and telling the processor unit that it will be notified when the request is completed. The processor unit is then free to go about its other business. Upon completion of the halt operation, the processor unit is notified of such event by way of a normal I/O interrupt.

The complete mechanism for performing the improved HALT DEVICE operation is described by the following logic statement: Asynchronous-Halt- Device:procedure(...