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Analog To Digital Test System

IP.com Disclosure Number: IPCOM000085813D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Schrecengost, LB: AUTHOR

Abstract

Test system 1 - 9 is used to calibrate analog-to-digital (A/D) converter units, e.g., unit 10.

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Analog To Digital Test System

Test system 1 - 9 is used to calibrate analog-to-digital (A/D) converter units, e.g., unit 10.

Output pulse Pt from clock 1 simultaneously triggers unit 10 and feeds amplitude converter 2. As a result, pulse gate generator 3 is triggered and simultaneously initiates two output pulses of different duration at its outputs a and
b. The not counterpart of the longer pulse is fed from output a to driver 4 which, in turn, provides a calibration pulse Ec of known amplitude and duration, e.g., 100 microns. The digital output, which for example is in binary-coded decimal (BCD) form, of unit 10 under test when gated on by pulse Pt is converted to an appropriate amplitude level by converter 5, from whence it is read out by an indicator, e.g., light-emitting diode (LED) character display 6. The output of converter 5 is also fed to an input of comparator 7.

The two outputs a, b of generator 3, i.e., the long and short output pulses, are exclusively OR'ed by logic 8 which provides an error detector signal Ed to the other input of comparator 7. It also provides an appropriate delay to compensate for late triggering of unit 10 and the slow response times of the associated operational amplifiers of converter 5.

If the output of unit 10 is not at the proper output level response for the given calibration pulse Ec, comparator 7 generates an error signal Ed' at its output which sets error indicator latch 9.

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