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Error Detector

IP.com Disclosure Number: IPCOM000085823D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Radcliffe, JK: AUTHOR

Abstract

Detector 1 tests bipolar binary signal Es for errors with respect to an expected value and stores the error detection, if any, at a high rate of speed.

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Error Detector

Detector 1 tests bipolar binary signal Es for errors with respect to an expected value and stores the error detection, if any, at a high rate of speed.

Signal Es is fed to one input of differential amplifier 2 of comparator stage 3. Amplifier 3 is biased by current source 4 and is compared with the reference signal Er applied to its other input. Cross-coupled latch 5, located in the collector circuit of amplifier 2, which is normally off, is gated ON by sample pulses from circuit source 6 and is set to the particular state of amplifier 2 at the time it is sampled. Thus, between samples, changes in the Es signal level effect only a small change across outputs Q, Q, then when sampled larger voltages appear across Q, Q.

Output stage 7 is a degenerated amplifier 8. It can be shown that by judiciously selecting the gain of stage 7 and the biases of current sources 9 - 11, currents Ia and Ib are greater than the output currents pf sources 10 and 11 when the differential value Ed of latch 5 is within a certain threshold range. Under these conditions, no error detection output signal appears at output terminal 12.

Likewise, if latch 5 is set at the binary state which is the same as the expected state value generated by the selectable current source 13, then no error detection signal appears at terminal 12. However, if latch 5 is set to a 0 state, and source 13 is selected to be in the 1 state value, then the action of shunt feedback (SF) circuit, shown sch...