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Impurity Gettering by Wafer Back Side Dislocations

IP.com Disclosure Number: IPCOM000085828D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Pliskin, WA: AUTHOR [+4]

Abstract

Metallic impurities suspected of degrading field-effect transistor (FET) and bipolar devices are gettered by deliberately introducing dislocations into the back side of silicon wafers. During subsequent wafer high-temperature processing, such as oxidation, diffusion, etc., metallic impurities preferentially locate at the damaged region leaving the front side of the wafer relatively free of such impurities for device processing.

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Impurity Gettering by Wafer Back Side Dislocations

Metallic impurities suspected of degrading field-effect transistor (FET) and bipolar devices are gettered by deliberately introducing dislocations into the back side of silicon wafers. During subsequent wafer high-temperature processing, such as oxidation, diffusion, etc., metallic impurities preferentially locate at the damaged region leaving the front side of the wafer relatively free of such impurities for device processing.

Dislocation damage is created on the wafer back side as follows:. The silicon wafer is covered with a thin thermal oxide and the oxide is removed from the back side. Approximately 1500 Angstroms of Si(3)N(4) is chemically vapor deposited on the wafer back side. The protective oxide is removed from the front side of the wafer and the desired devices are formed thereon in the usual manner.

The stresses created by the deposition of the Si(3)N(4) on the silicon are relieved by the generation of dislocations during the high-temperature heat cycles associated with semiconductor device processing. The Si(3)N(4) can be removed after the final high-temperature step.

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