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Front Side Edge Dislocation Gettering of Silicon Wafers

IP.com Disclosure Number: IPCOM000085829D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Deines, JL: AUTHOR [+4]

Abstract

Edge dislocations are deliberately introduced into the front side of silicon wafers to efficiently getter metallic impurities, which degrade desired field-effect transistor (FET) and bipolar devices formed on the wafer front side. Patterned Si(3)N(4) is deposited on the wafer front side so that the edges of the Si(3)N(4) are as close as is permissible to the locations where the desired devices are to be formed. The stresses created by the patterned deposition of the Si(3)N(4) on the silicon are relieved by the generation of edge dislocations, during the high-temperature heat cycles associated with semiconductor device processing.

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Front Side Edge Dislocation Gettering of Silicon Wafers

Edge dislocations are deliberately introduced into the front side of silicon wafers to efficiently getter metallic impurities, which degrade desired field-effect transistor (FET) and bipolar devices formed on the wafer front side. Patterned Si(3)N(4) is deposited on the wafer front side so that the edges of the Si(3)N(4) are as close as is permissible to the locations where the desired devices are to be formed. The stresses created by the patterned deposition of the Si(3)N(4) on the silicon are relieved by the generation of edge dislocations, during the high- temperature heat cycles associated with semiconductor device processing.

In the example given in the figures, normal processing is followed until post epi reoxidation to yield the structure shown in Fig. 1. The second P+ isolation is deposited and driven in as shown in Fig. 2. Next, a "block out" mask to cover the entire isolation and device area plus an additional 1-2 micron "safety" region is added as shown in Fig. 3. The safety region prevents the Si N generated dislocations from penetrating the device junctions. The epi oxide is etched down to the silicon surface and the Si(3)N(4) is then deposited as shown in Fig. 4. Conventional processing steps are used to complete the desired devices.

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