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High Speed Comparator

IP.com Disclosure Number: IPCOM000085838D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Debord, P: AUTHOR [+2]

Abstract

This is a high-speed comparator performing a latching function.

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High Speed Comparator

This is a high-speed comparator performing a latching function.

The circuit comprises two dotted differential amplifiers. The first amplifier includes a current source I, two transistors T1, T2, respectively, loaded by transistors T3, T4 and driving emitter-followers T5, T6. The second amplifier comprises transistors T7, T8, T10 connected to the first amplifier at points A, B and C and therefore shares the same output stage T3, T4, with it, while being driven by T5, T6.

In operation, transistor T10 is normally ON while transistor T9 is OFF by connecting the base of T9 to ground level and the base of T10 to a positive reference voltage VREF''. The nodes E and F keep indefinitely the logic state which corresponds to the preceding comparison. When a new comparison is to be performed, the current switch T9, T10 is operated by applying a positive strobe level higher than VREF'' to the base of T9. Thus T9 is turned ON and T10 OFF. The first differential amplifier is in operation and either T1 or T2 is turned ON, depending upon the level of the analog input as compared to the fixed reference voltage Vref. The logic levels of nodes E and F are conditioned by the operating state of the first differential amplifier.

On the falling edge of the strobe pulse, T10 is turned ON and T9 OFF. This circuit is latched by having the second differential amplifier store the respective logic situation of nodes E and F.

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