Browse Prior Art Database

TTL Circuit with Improved Noise Margins

IP.com Disclosure Number: IPCOM000085842D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

A basic TTL circuit consists of an input multiemitter transistor T1 (Fig. 1), whose collector is connected to the base of an output transistor T2. Emitters E1, E2, E3 of T1 form the logic inputs, and the collector of T2 forms the logic output 0. Current is supplied via current sources I1, 12 and 13 connected to the base of T1, the collector of T2 and the base of T2.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

TTL Circuit with Improved Noise Margins

A basic TTL circuit consists of an input multiemitter transistor T1 (Fig. 1), whose collector is connected to the base of an output transistor T2. Emitters E1, E2, E3 of T1 form the logic inputs, and the collector of T2 forms the logic output
0. Current is supplied via current sources I1, 12 and 13 connected to the base of T1, the collector of T2 and the base of T2.

It is disadvantageous that a high-parasitic current Ip flows into emitter E1 when T1 is highly saturated, and E2 and/or E3 is at the lower and E1 at the upper switching level. The parasitic current Ip is a function of the inverse current amplification beta i, thus Ip = beta i . I1.

To ensure satisfactory noise margins and high-switching speeds, the parasitic current Ip and the saturation voltage of T1 have to be reduced. To this end an additional transistor T3 is employed which is complementary to T1 and which reduces the effective inverse current amplification of T1.

The emitter-base voltage of T3 is parallel to the base-collector voltage of T1 and is chosen in such a manner that in the stationary state, as large a part as possible of I1 is discharged via T3. The collector of T3 is connected either to a fixed voltage potential or to the collector of T1. These measures ensure that the base current of T1 and thus Ip is reduced considerably during saturation.

A capacity Cp implemented between the base and collector of T1 leads to a high switch-off speed of T2. Cp is obtained automatically by charg...