Browse Prior Art Database

PLA Driver with Integral Race Prevention

IP.com Disclosure Number: IPCOM000085846D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Delahanty, RJ: AUTHOR [+3]

Abstract

The figure shows a synergistic combination of a metal-oxide semiconductor , (MOS) varactor as disclosed at P.1365 of IEEE Proceedings Sept. 1971, with a programmed logic array (PLA) input bit partitioning circuit. Timing signals T and T are provided to the PLA chip. These timing signals are utilized to gate inputs A and B to the array through nodes 11-14 as the four possible logical combinations of A and B.

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PLA Driver with Integral Race Prevention

The figure shows a synergistic combination of a metal-oxide semiconductor , (MOS) varactor as disclosed at P.1365 of IEEE Proceedings Sept. 1971, with a programmed logic array (PLA) input bit partitioning circuit. Timing signals T and T are provided to the PLA chip. These timing signals are utilized to gate inputs A and B to the array through nodes 11-14 as the four possible logical combinations of A and B.

Because of variations in the propagation delays in the various logic paths, a delay is required before the combinations of A and B are presented to the array. Also because the array itself appears as a capacitive load, driving field-effect transistors (FET's) 21-24 are required to drive the array.

Voltage level shifting capacitors 31-34, referred to as bootstrap capacitors in the cited reference, provide the extra voltage necessary to fully saturate drivers 21-24 when FET 25 conducts. One plate of capacitors 31-34 is formed by a field induced inversion region at the surface of the silicon beneath the metallization and oxide layers. The inversion region overlaps the drains of FET's 21-24 and the metallization layer is nodes 11-14 which is connected to the gates of FET's 21-24.

The circuit takes advantage of the fact that only one of the four possible logical combinations of A and B can be met at any one timing cycle to insure a reliable binary delay state, and utilizes the MOS varactor characteristic to decouple the capa...