Browse Prior Art Database

Two Device Per Bit, Precharged ROS With Differential Sensing

IP.com Disclosure Number: IPCOM000085853D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+2]

Abstract

A two device per bit read-only storage (ROS) cell and a simplified output latch speeds up access time and eliminates the need for a read-enable clock. A single clock precharges common drain lines; grounds the bit 1 and 0 lines and gates the address circuitry to achieve a high speed ROS with some trade off to power dissipation and chip area.

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Two Device Per Bit, Precharged ROS With Differential Sensing

A two device per bit read-only storage (ROS) cell and a simplified output latch speeds up access time and eliminates the need for a read-enable clock. A single clock precharges common drain lines; grounds the bit 1 and 0 lines and gates the address circuitry to achieve a high speed ROS with some trade off to power dissipation and chip area.

Fig. 1 shows a two device field-effect transistor (FET) ROS array 10 having a common drain line 12 for each row and bit 1 and bit 0 lines. FET devices are connected between the bit 1 line and line 12 or bit 0 line and line 12 depending upon the information to be stored at the intersection of a column line C1, C2...CN and a row R1...RN. As one example, an FET 14 is connected between the bit 1 line and line 12 to store a binary 1 at the cross-point R1, CN. As another example, an FET 16 is connected between the bit 0 line and line 12 to store a binary 0 at the cross-point RN,CN.

Column lines C1...CN are connected at one end to gate drivers 18 which are selected by decode circuit 20 driven by true/complement drivers 22. Decode gating devices 24 are associated with each column to prevent incorrect addresses from addressing the array 10.

The bit lines for each row are connected at one end to a sense latch 26, as shown in Fig. 2, and at the other end to gating devices 28 which are controlled by a restore clock 30. The drain lines 12 are energized from a supply 32 through an isolating device 34 which is also activated by the clock pulse line 30.

When the restore pulse 30 is down, the device 34 turns off to retain the lines 12 in a charged condition. The devices 28 are also turned off which isolate the bit 1 and bit...