Browse Prior Art Database

Selective Data Acquisition System

IP.com Disclosure Number: IPCOM000085866D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Boyd, KW: AUTHOR [+2]

Abstract

The apparatus of the drawing receives signals from a test subject 2 and records the signals on a magnetic tape cassette 3. Test subject 2 provides signals on a number of output lines represented by lines 4 and 5. The line that is to be sampled is identified by an address on a line 6 that is formed by an address generator 7. Address generator 7 receives a timing signal from a clock 8 to cycle through the addresses in a selected sequence.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Selective Data Acquisition System

The apparatus of the drawing receives signals from a test subject 2 and records the signals on a magnetic tape cassette 3. Test subject 2 provides signals on a number of output lines represented by lines 4 and 5. The line that is to be sampled is identified by an address on a line 6 that is formed by an address generator 7. Address generator 7 receives a timing signal from a clock 8 to cycle through the addresses in a selected sequence.

An analog multiplexer 9 receives the inputs from the test subject 2 and receives the address on line 6, and it produces the analog input of the selected line at its output. An analog-to-digital converter 10 receives the output of analog multiplexer 9 and produces the corresponding digital output on output line 11.

The digital output on line 11 can be stored temporarily in a scratch pad memory 12 and this value is called the present value of the test subject signal. The address on line 6 is stored with the present value to identify the test value. The present value and address can also be transferred through buffer and interface circuits 14 and stored on the tape cassette 3.

Tape cassette 3 provides an input to circuit 14 when it is up to speed and ready to store data. During the test on subject 2, the system stores successive significant values of each signal and buffer and interface circuits 14 receive a time signal from clock 8 that is recorded with each signal, to show the succession of signals...