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Arithmetic Shift

IP.com Disclosure Number: IPCOM000085876D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 9 page(s) / 124K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

The shifter shown is a 3-stage 32-bit parallel right rotator which implements several shift and rotate commands. A right shift is achieved by controlling the second stage to allow only shift paths and blocking end-around paths. A left shift is achieved by specifying the shift code in 2's complement form and, again, controlling the appropriate shift paths of the second stage. The inputs and outputs consist of: BIT 0 through BIT 31 - input data high-to-low order, respectively. DATA 0 through DATA 31 - output data high-to-low order, respectively. (S16, S8, S4, S2, S1) - 5-bit shift code specifying the amount of right rotation. (IM3, IM2, IM1) - command code.

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Arithmetic Shift

The shifter shown is a 3-stage 32-bit parallel right rotator which implements several shift and rotate commands. A right shift is achieved by controlling the second stage to allow only shift paths and blocking end-around paths. A left shift is achieved by specifying the shift code in 2's complement form and, again, controlling the appropriate shift paths of the second stage.

The inputs and outputs consist of: BIT 0 through BIT 31 - input data high-to-low order, respectively.

DATA 0 through DATA 31 - output data high-to-low order, respectively. (S16, S8, S4, S2, S1) - 5-bit shift code specifying the amount of right rotation. (IM3, IM2, IM1) - command code.

The following commands are implemented: COMMAND CODE CODE
IM3 IM2 IM1 NAME 0 1 1 ZS = Zero Shift

1 0 0 SLL = Shift Left Logical

1 0 1 SRL = Shift Right Logical

1 1 0 SRA = Shift Right Arithmetic

1 1 1 ROTR = Rotate Right

For the remaining command code combinations (000, 001, 010) the shifter produces 0's on the data output lines.

The 5-bit shift code, S16, S8, S4, S2, and S1, specifies the amount of right rotate. The first stage of the right rotator is controlled by S1 to effect a 0 or a right 1 rotation. The second stage is controlled by S4 and S2 to effect a 0, 2, 4, or 6 right rotation. The third stage is controlled by S16 and S8 for a 0, 8, 16, or 24 right rotation.

During ZS (Zero Shift), the shift code is ignored and the outputs DATA 0 through 31 equal BIT 0 through 31, respectively.

During ROTR (Rotate Right), the shift code effects a right rotation without any additional controls.

During SRL (Shift Right Logical), the shift code again effects a right rotation. However, ALLOW control signals allow only the shift paths to be open and block the end-around paths.

During SLL (Shift Left Logical), the shift code is the two's complement of the desired left shift so that a right rotation can again be used together with appropriate ALLOW control signals. For example, to achieve a left rotation of 18, the two's complement of the shift code is specified (32-18=14) which is used to perform a right rotate. The effect of rotating right 14 positions is the same as rotating left 18 positions. The only exception to the two's complement shift code for left shift is the shift code of zero, i.e., S16.S8.S4.S2.S1, which will be referred

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to as ZERO. For SLL it represents the true value of zero shift and not 32-0=32 shift.

During SRA (Shift Right Arithmetic), the shift code and the ALLOW signals perform the same function as during an SRL (Shift Right Logical) with the following added feature: The high-order input bit, BIT 0, is forced in all DATA bit positions which have entered via end-around paths. For example, if BIT 0 is 1, and the shift code is 5, then DATA 0 through DATA 4 will be 1 since they originated in BIT 27 through BIT 31, respectively. The added control signals, labeled FORCE, perform this feature. The command SRA is used for propagating the algebraic...