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Digital Filter Circuit for Noisy Lines

IP.com Disclosure Number: IPCOM000085902D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Eggebrecht, LC: AUTHOR

Abstract

The circuit of the figure may be used to filter noise from any digital line. The circuit will only pass a signal which remains active or inactive for a specified time, and will not transmit any pulse which remains active or inactive for less than a specified time.

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Digital Filter Circuit for Noisy Lines

The circuit of the figure may be used to filter noise from any digital line. The circuit will only pass a signal which remains active or inactive for a specified time, and will not transmit any pulse which remains active or inactive for less than a specified time.

Inverter 11 and capacitor 12 isolate the circuit from the line 13 and filter high frequency negative going noise spikes. Inverter 14 and capacitor 15 are used to filter high frequency positive noise spikes. Inverter 16 is used to reshape the signal after the integrating circuits. The size of capacitors 12 and 15 is chosen such that they will effectively filter noise which is less than twice the TD (Time Delay) value in pulse width. This ensures that only noise of sufficient pulse width to operate the pulse rejection circuit is passed.

The purpose of TD 17 and exclusive OR 18 is to generate a pulse for every transition positive or negative, noise or signal. The consecutive transition signal on line 19 is used to fire a single-shot 20 for a specified time, SS1. The time duration SS1 determines the pulse width or noise size that will be rejected. The back edge of the single-shot pulse is used to clock a `D' type flip latch 22. The latch samples and sets to the status of the input line. The circuit ensures that the `D' type flip latch 22 will only assume the status of the input line 13 if the transition was the result of a signal longer than SS1 time.

A problem arises...