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Pulse Synchronization Circuit

IP.com Disclosure Number: IPCOM000085904D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Carter, DW: AUTHOR

Abstract

Pulse synchronization circuit 10, Fig. 1 includes inverter 11 for inverting oscillator pulses (+OSC), Fig. 2, whereby latch LT1 is set, when start line 12 goes active, by the negative level of an oscillator pulse. Latch LT2 thereafter sets when the oscillator pulse goes positive. The output is taken from AND circuit 13. Any short pulses generated by astability of latches LT1 or LT2 are blocked from the output, by the negative level of the oscillator pulse at AND circuit 13.

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Pulse Synchronization Circuit

Pulse synchronization circuit 10, Fig. 1 includes inverter 11 for inverting oscillator pulses (+OSC), Fig. 2, whereby latch LT1 is set, when start line 12 goes active, by the negative level of an oscillator pulse. Latch LT2 thereafter sets when the oscillator pulse goes positive. The output is taken from AND circuit 13. Any short pulses generated by astability of latches LT1 or LT2 are blocked from the output, by the negative level of the oscillator pulse at AND circuit 13.

This synchronization circuit can be used as a clock synchronizer or as a low- resolution timer.

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