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Microprocessor High Speed ALU Input Buffer with Data Save and Restore Capability

IP.com Disclosure Number: IPCOM000085905D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Eggebrecht, LC: AUTHOR

Abstract

The circuit of the figure shows select lines 11 for gating data onto a bus 13, which conventionally would load a register 14 for transmission on bus 15 to the processor arithmetic and logic unit (ALU). Included in the figure is a bypass control line 17 which enables one of the AND blocks 18 and 19. Use of the bypass mode of operation enables the data on bus 13 to be transmitted to the ALU simultaneously with the writing of register array 14.

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Microprocessor High Speed ALU Input Buffer with Data Save and Restore Capability

The circuit of the figure shows select lines 11 for gating data onto a bus 13, which conventionally would load a register 14 for transmission on bus 15 to the processor arithmetic and logic unit (ALU). Included in the figure is a bypass control line 17 which enables one of the AND blocks 18 and 19. Use of the bypass mode of operation enables the data on bus 13 to be transmitted to the ALU simultaneously with the writing of register array 14.

Accordingly, the ALU is operating on the data while the register is being written. This mode of operation can reduce the time duration associated with writing data from bus 13 to register 14 and reading data out of register 14 in the conventional hardware design by two thirds in a typical case.

In an alternate mode of operation, this circuit may be used to automatically save and restore data while performing ALU operations. When the bypass mode is selected, data may be gated directly to the ALU while data in the register 14 is restrained with the capability of being restored thereafter.

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