Browse Prior Art Database

Address Translator for Small Computers

IP.com Disclosure Number: IPCOM000085906D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Hicks, DR: AUTHOR

Abstract

A requirement frequently exists for a larger address space than that provided by the word length of small data processors, typically 16 bits.

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Address Translator for Small Computers

A requirement frequently exists for a larger address space than that provided by the word length of small data processors, typically 16 bits.

Fig. 1 shows a microprocessor-based system 100 having a 16-line address bus 101 and an 8-line bidirectional data bus 102. Via these buses, processor 110 is coupled to conventional local registers 120 and I/O device adapters 130. Main storage 140, however, receives a 20-bit address 103 from address translator 200, which receives a 16-bit address from bus 101. Translator 200 also receives a 6-bit I/O address 104 from adapter 104 and 8-bit data from bus 102.

Shown in more detail in Fig. 2, address translator 200 includes a bank 210 of sixteen 32-bit registers. A 4-bit "segment" portion 221 of the 16-bit incoming address in register 220 enables read selector 230 to address one of the registers 210. A 20-bit "base" field 211 from the addressed register is combined with a 12- bit "displacement" field 222 in adder 240, to produce the effective address 103 for main storage 140, Fig. 1.

Comparator 250 simultaneously produces an error signal 251 if dis displacement 222 exceeds the value of a 12-bit "bound" field 212 from the addresses register in bank 210. Signal 251 may be used as desired to inhibit storage 140, to provide an interrupt or status indication to pro processor 110 and so forth. In this way, translator 200 provides for variable-length segments in storage 140, which segments may begi...