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Compute Subscript Address Instruction

IP.com Disclosure Number: IPCOM000085909D
Original Publication Date: 1976-Jun-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 47K

Publishing Venue

IBM

Related People

Bains, RL: AUTHOR [+4]

Abstract

A special instruction called Compute Subscript Address (CSA) enables the address of any data element in an array of like data elements to be computed by executing only this one instruction. The CSA instruction has a format shown in Fig. 1.

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Compute Subscript Address Instruction

A special instruction called Compute Subscript Address (CSA) enables the address of any data element in an array of like data elements to be computed by executing only this one instruction. The CSA instruction has a format shown in Fig. 1.

The second operand is reduced by one and multiplied by the third operand. The product of this multiplication is added to the first operand and the sum is placed in the first operand location. The second operand is unchanged by the operation.

The first operand is treated as the offset portion of a virtual address. The second and third operands are treated as 16-bit unsigned binary integers. The second operand, which occupies two bytes in storage, is reduced by a value of one and multiplied by the contents of the I field from the instruction. This product, which is considered to be a 16-bit unsigned binary integer, is then added to the contents of the halfword register designated by R1, and the sum replaces the contents of the register.

The instruction stream, Fig. 2, which contains the CSA instruction, and the data array are contained in the system Main Storage Unit (BSM). The instruction stream is processed by the Central Processing Unit (CPU) which contains the following facilities: 1. Instruction Buffer Register 1 - used to buffer the first 4 bytes of the instruction that is currently being processed. 2. Instruction Buffer Register 2 - used to buffer the remaining bytes of the instruction that is currently being processed. 3. IAR1 - contains the BSM address of the next instruction to be executed. 4. IAR2 - IAR backup register. 5. A-Register, B-Register - LSR Array Address Register. 6. C-Register - LSR Array Address Limit Register. 7. D- Register - contains the length of the instruction currently being executed. 8. LSR Array - contains the architected base registers that are used by the programmer.
9. ALU - performs arithmetic and logical operations on one or two input operands. The capability to increment or decrement an input operand by a constant value of 1, 2 or 4 is available.

Execution of the CSA instruction by the CPU is described below. Note that the instruction stream has the following general characteristics:
1. The first 4 bits of each op-code byte contain the length of the instruction expressed as an unsigned binary number.
2. All register address fields are 4 bits.
3. All displacement fields are 12 bits.

For purposes of illustration, the following assumptions are made regarding the subject instruction and instruction parameters. 1. Subject Instruction Length = 6 bytes 2. R1 = 1 3. Operand 2 = 3 4. I3 = 3

By specifying a value of 1 for R1, it is the intention of the programmer to have the CPU compute the effective address of the array element and store it in Base Register 1.

1

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CPU Execution Sequence:
1. IAR1 contains the address of the

CSA instruction. This address was set up during the execution of the previous instruction.

Hence, t...