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Simultaneous Internal Probing on Multilevel Semiconductor Integrated Circuitry

IP.com Disclosure Number: IPCOM000085989D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Chamberlin, PD: AUTHOR [+2]

Abstract

Subsequent to the first level of metallurgy on an integrated semiconductor chip a layer of passivating polymer, e.g., polyimide 1 is applied. Using well known photolithography techniques via holes are formed in the polyimide 1 of Fig. 1 where the substrate 2 and a first level metallurgy 3 and the polyimide are subjected to final cure.

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Simultaneous Internal Probing on Multilevel Semiconductor Integrated Circuitry

Subsequent to the first level of metallurgy on an integrated semiconductor chip a layer of passivating polymer, e.g., polyimide 1 is applied. Using well known photolithography techniques via holes are formed in the polyimide 1 of Fig. 1 where the substrate 2 and a first level metallurgy 3 and the polyimide are subjected to final cure.

Fig. 2 illustrates the next step of depositing second level metallurgy 4, e.g., chrome-copper-gold or any other suitable metal which is etched to form the configuration of Fig. 3. Wafers are then subjected to RF oxidization treatment which removes all the polymer except that which is masked by the metal land 4 of Fig. 3. This procedure results in the configuration of Fig. 4, whereby the first and second level metal lands 3 and 4 are accessible to probing while remaining insulated.

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