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Latch Current Switch

IP.com Disclosure Number: IPCOM000086014D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Buckley, F: AUTHOR [+2]

Abstract

Latch switch (SW) 11 is of the polarity-hold type. With a positive pulse applied to W1, the output current at output J11 assumes a state indicative of the polarity applied to its input B1. Input B1 is selectably connected by schematically shown switch 1 to the positive and negative terminals of a bipolar current circuit 2, shown by way of example, as two independent current sources 3, 4. Transistors Q1 and Q2 are configured as an emitter-coupled pair. The collector of Q1 is connected to the base Q2 through a positive feedback path, i.e., conductors 5, 6. The magnitude of voltage source S is greater than that of voltage source P.

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Latch Current Switch

Latch switch (SW) 11 is of the polarity-hold type. With a positive pulse applied to W1, the output current at output J11 assumes a state indicative of the polarity applied to its input B1. Input B1 is selectably connected by schematically shown switch 1 to the positive and negative terminals of a bipolar current circuit 2, shown by way of example, as two independent current sources 3, 4. Transistors Q1 and Q2 are configured as an emitter-coupled pair. The collector of Q1 is connected to the base Q2 through a positive feedback path, i.e., conductors 5, 6. The magnitude of voltage source S is greater than that of voltage source P.

Assume latch 11 is in a binary "1" state, i.e., Q1 is off and Q2 is on, and that the control voltage Elo at input W1 is in the low or quiescent state (Elo<P). The resultant currents through R1 and R2 are small; therefore, the voltages Va, Vb at nodes a and b are substantially at Elo and S, respectively.

To write a "0", switch 1 is first set to the negative terminal of circuit 2 insuring that diode D3 is on and Q3 is off. As the voltage at W1 begins to rise from its low state to its high state Ehi, it rises above S, Va exceeds Vb and positive feedback causes Q1 to turn on and saturate. This situation is maintained as the voltage at W1 returns to its quiescent state, i.e., Elo. As a result, Q2 is now off and the output current at terminal J11 is substantially zero.

To write a 1, B1 is first set to a large positive value, i.e., positive terminal of source 2. Thus, as the voltage at W1 rises from Elo to Ehi, node a is clamped at a voltage close to P. The base of Q2 tracks the voltage at W1 because of diode D1, and as Vb appro...