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Browse Prior Art Database

One Device Storage Cell With Implanted Storage Node

IP.com Disclosure Number: IPCOM000086022D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Klepner, SP: AUTHOR

Abstract

A one-device memory cell having an N-type storage node is produced using silicon gate technology and ion implantation, while requiring only a single polysilicon deposition step and a single polysilicon etching step. Conventional processing results in an inversion storage node which is considered less desirable.

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One Device Storage Cell With Implanted Storage Node

A one-device memory cell having an N-type storage node is produced using silicon gate technology and ion implantation, while requiring only a single polysilicon deposition step and a single polysilicon etching step. Conventional processing results in an inversion storage node which is considered less desirable.

In Fig. 1, P substrate 1 is covered by thin oxide 2 in storage cell area 3 and thick oxide 4 elsewhere. The entire structure is covered by photoresist 5, except that a portion of area 3 is uncovered where the storage node of the cell is to be formed. Arsenic or phosphorus ions are implanted in the uncovered substrate 1 to create an N-type surface skin 6.

Polycrystalline silicon 7 and 8 of Fig. 2 are formed from a single deposition step and a single etching step, following which self-aligned N/+/ diffusions 9 and 10 of Fig. 3 are made to complete the storage cell structure, consisting of a field- effect transistor (FET) switch (7, 9, and 10) and a storage capacitor (8, 2, and 6).

Fast FET circuitry contains depletion mode transistors. If the circuit design permits, the same ion implant step that creates N skin 6 may also serve as the channel implant of depletion mode transistors elsewhere on the chip.

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