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Virtual Memory Addressing in an Input Output Channel

IP.com Disclosure Number: IPCOM000086037D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 27K

Publishing Venue

IBM

Related People

Covington, RP: AUTHOR [+3]

Abstract

This technique extends the virtual memory addressing scheme of the central processing unit (CPU) to the I/O channel in a processing system. In virtual memory addressing, there must be at least one separate channel control word (CCW) for each I/O operation. The requirement for multiple operations on behalf of different tasks is solved by the present technique, by adding a new field identified as "segment table pointer" to the typical field contained in a CCW.

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Virtual Memory Addressing in an Input Output Channel

This technique extends the virtual memory addressing scheme of the central processing unit (CPU) to the I/O channel in a processing system. In virtual memory addressing, there must be at least one separate channel control word (CCW) for each I/O operation. The requirement for multiple operations on behalf of different tasks is solved by the present technique, by adding a new field identified as "segment table pointer" to the typical field contained in a CCW.

In order to make more efficient use of memory and control the sharing of data and programs among different tasks, data processing systems use virtual addressing. This means that the address that a central processing unit (CPU) uses in referencing main memory are translated before they reach the memory. This translation is done by looking up an entry in a segment table. In multiprogramming systems, there are typically many segment tables, at least one for each task in the system, although the CPU only uses one segment table at a time.

In architectures which have virtual addressing today, such as the IBM System 360/67 and the IBM System 370's, the CPU(s) use virtual addresses but the I/O channels do not. This requires software to translate a virtual address of a task's I/O data buffer to a real address before the data can be read or written by the channel. It is desirable to avoid this translation step of converting from the virtual addressing scheme used by software to the real addressing scheme used by the channel, because it represents overhead in the system.

Associated with each task is a program status word (PSW) which contains a pointer to the segment table used for that task. (This PSW also contains other data such as the current instruction address and protection information.) Whenever the CPU switches from one task to another, it also switches PSW's. Thus, the CPU always has a pointer to the segment table for the task being executed. However, the problem of identifying which table the channel should use is much more complicated, for the following reasons: 1. Channel operation is concu...