Browse Prior Art Database

Interactive Graphics for Wiring

IP.com Disclosure Number: IPCOM000086039D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Habra, RR: AUTHOR

Abstract

In the process of designing a chip, a major part of the effort involves wiring additions and modifications until the entire part number is 100% wired with all technology ground rules met. Present available wiring aids include working drawings where the actual wiring is shown, as well as available and blocked channels. The user would then mark up his drawings with the necessary modifications, transcribe them into a wiring language and resubmit his job for checking. That process is repeated several times until the design automation system comes up with zero errors. This is time consuming and error prone.

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Interactive Graphics for Wiring

In the process of designing a chip, a major part of the effort involves wiring additions and modifications until the entire part number is 100% wired with all technology ground rules met. Present available wiring aids include working drawings where the actual wiring is shown, as well as available and blocked channels. The user would then mark up his drawings with the necessary modifications, transcribe them into a wiring language and resubmit his job for checking. That process is repeated several times until the design automation system comes up with zero errors. This is time consuming and error prone.

The proposed interactive graphics wiring (IGW) program will greatly simplify the task of embedding those overflow wires, and minimize the time it takes to complete the design of a chip.

By using a terminal with the IBM TSO program on an IBM 370 system, the IGW program can display on the screen any portion of the chip and allows the user to make additions and deletions to the wiring. The net under modification is instantaneously checked for any technology ground rules violations. Some of the checks performed include the following: 1. Intersection check, such as two nets shorting together, or a net wired in a forbidden region such as power busses or circuit area. 2. A logical to physical check to ensure that the initial logic has indeed been all wired. 3. Continuity check for every net under modification. 4. Antennas: They are redundant wires and occupy...