Browse Prior Art Database

Level Converter Circuit

IP.com Disclosure Number: IPCOM000086045D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+2]

Abstract

This is a converter circuit for converting one set of binary logic voltage levels to a different set of binary logic voltage levels.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Level Converter Circuit

This is a converter circuit for converting one set of binary logic voltage levels to a different set of binary logic voltage levels.

The input to the circuit is adapted to receive a voltage swing of 1.8 volts from a downlevel of +V1 volts to an uplevel of +V2 volts. The output of the circuit is designed to provide a voltage swing of approximately 1.2 volts with the uplevel at ground potential. The input is received at the emitters of input transistor T1 and coupled through transistor T2 providing an inverted signal at intermediate node
A. This inverted signal is inputted to the base of emitter-follower transistor T3 and through diodes D1 and D2 to the base of multiemitter transistor T4.

Transistor T4 inverts the signal again providing an inphase output at the output node. The load resistor RL is connected to ground potential providing a zero volt output when transistor T4 is off. When transistor T4 is on, a negative potential (-V1) is provided at the output node. To improve the speed of operation, all transistors are clamped by Schottky barrier diodes.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]