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Read Only Store Checking for Reliability

IP.com Disclosure Number: IPCOM000086048D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Nicoletti, MA: AUTHOR

Abstract

This is a technique for checking data processing systems that are read-only store (ROS) controlled and have no parity checking.

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Read Only Store Checking for Reliability

This is a technique for checking data processing systems that are read-only store (ROS) controlled and have no parity checking.

ROS reliability data checking is performed while the system is in its "wait state loop" (which would be 50% of the time). Two ROS addresses are used in the wait state (Fig. 1). ROS address 1 contains all 0's and ROS address 2 contains all 1's. If there are no pseudo addresses active, the system continuously self-checks for correct ROS data transmissions and receiving 1's and 0's.

While the system is in a wait state, the loop is between the two ROS addresses. During ROS address 1's machines cycle (Fig. 2), the code point decoders on each large-scale integrated (LSI) chip decodes the ROS data field as an all 0's input. Similarly during ROS address 2's cycle, all 1's are decoded. These two code points are ORed together and their outputs are dotted with other LSI chips that have identical logic for 0's and 1's detection.

If any chip fails, the condition is latched as a ROS data failure, which activates the machine check pseudo address. This pseudo address is sampled as the next ROS address (through the interrupt hardware). The machine check handler at level zero can determine the error's source. This information can be stored in a log area that is used for preventive maintenance or some other appropriate action can be taken.

Fig. 3 shows a ROS that is controlling LSI chips without data bit checking. A...