Browse Prior Art Database

Pseudo Self Aligned Gate FET

IP.com Disclosure Number: IPCOM000086050D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

Aluminum, Al, gate field-effect transistors (FETs) have high gate-source and gate-drain overlap capacitance. The following process utilizing porous silicon, Si, produces a Al gate FET with low-overlap capacitance.

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Pseudo Self Aligned Gate FET

Aluminum, Al, gate field-effect transistors (FETs) have high gate-source and gate-drain overlap capacitance. The following process utilizing porous silicon, Si, produces a Al gate FET with low-overlap capacitance.

The process sequence for an N channel version involves the growth of a thick silicon dioxide layer upon a P silicon <100> oriented substrate. Openings are made in the silicon dioxide by standard photolithography for the source and drain diffusion step. The N+ diffusion is made using phosphorous or arsenic as the impurity. Without growing any silicon oxide over the N+ source-drain regions, the top layer of N+ regions is made porous with anodically etching in hydrofluoric acid.

The thick silicon dioxide is removed from the channel region to produce the structure of Fig. 1, wherein the P silicon substrate 10 has a silicon dioxide layer 12 thereon, source and drain regions 14 and 16, with porous silicon surfaces 18 and 20 therein. The gate silicon dioxide is thermally grown to produce oxide layer 22. During the gate oxide growth, the porous silicon regions are formed into thick films 24 and 26 of SiO(2) with K < 3.9.

Phosphosilicate glass, not shown, is deposited on the surface of the gate oxide 22 and annealed at an elevated temperature. Contact openings, not shown, are made through the porous silicon dioxide films 24 and 26 to source and drain regions 14 and 16. Metal contacts, not shown, are formed to regions 14 and 16 and fo...