Browse Prior Art Database

High Capacitance, One Device Memory Cell

IP.com Disclosure Number: IPCOM000086051D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

The signal that is read out of a one-device metal-oxide semiconductor field-effect transistor (MOSFET) memory cell is proportional to: 1/(1 + C(BS) over C(N)) where C(BS) is the bit/sense line capacitance and C(N) is the storage node capacitance. Figs. 1 and 2 show two versions of the one-device cell.

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High Capacitance, One Device Memory Cell

The signal that is read out of a one-device metal-oxide semiconductor field- effect transistor (MOSFET) memory cell is proportional to: 1/(1 + C(BS) over C(N)) where C(BS) is the bit/sense line capacitance and C(N) is the storage node capacitance. Figs. 1 and 2 show two versions of the one-device cell.

C(j) is increased by using porous silicon technology. The diffusion on the storage node can be made very deep using porous silicon processing. This increases C(j).

Increasing X(j) in the storage node from 1 to 5 or 10 mu increases C(j) by about 2 or 3 times, respectively. The increase in C(N) increases the readout signal from the memory cell. The region which will contain the N+ node diffusion is made porous prior to the source-drain diffusion. At the end of the process, the metallurgical junction lies in the single-crystal silicon due to lateral diffusion.

Fig. 3 shows the version of Fig. 1 that can be made using this process, wherein the P substrate 10 has source-drain regions 12 and 14 with the central portion 16 of region 14 being composed of porous silicon.

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