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Browse Prior Art Database

Pseudo Via Process for Improved Planarization

IP.com Disclosure Number: IPCOM000086060D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Agnihortri, RK: AUTHOR [+2]

Abstract

In conventional sputtered deposition of quartz coatings 1 over land patterns 2 on integrated circuits 4 (see Fig. 1A), peaks 3 of quartz result over the metallization lines as illustrated in Fig. 2B. Normal formation of via holes 5 results in the retention of residual quartz peaks 6 on the land patterns which require overetching for their removal. This results in significant problems with increased circuit density.

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Pseudo Via Process for Improved Planarization

In conventional sputtered deposition of quartz coatings 1 over land patterns 2 on integrated circuits 4 (see Fig. 1A), peaks 3 of quartz result over the metallization lines as illustrated in Fig. 2B. Normal formation of via holes 5 results in the retention of residual quartz peaks 6 on the land patterns which require overetching for their removal. This results in significant problems with increased circuit density.

A solution shown in Figs. 2A-2D employs the use of a via pattern in a resist coating 7 over the metallization 2. This is followed by etching of the lands 2 to reduce their thickness into a concave-like land structure 2A. The land etching is correlated to the quartz peaks 3 normally obtained.

After etching, the resist coating 7 is removed and fabrication proceeds in the usual manner with sputtering on a quartz layer 1A of improved planarization, and formation of via holes 5A devoid of quartz peaks and with no need for overetching.

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