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Programmable Logic Array Logic Enhancement

IP.com Disclosure Number: IPCOM000086095D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Brickman, NF: AUTHOR [+3]

Abstract

The AND and 0R arrays 10 and 12 are separated by a programmable inverter array 14.

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Programmable Logic Array Logic Enhancement

The AND and 0R arrays 10 and 12 are separated by a programmable inverter array 14.

The programmable inverter consists of a programmable bit 16 and an exclusive OR circuit 18. When a `1' is personalized in the bit column 16, the corresponding input to the exclusive OR 18 is high, and this exclusive OR will act as an inverter. On the other hand, if a `0' is personalized, the corresponding input to the exclusive OR 18 is low, and this exclusive OR will act as a short circuit or a buffer driver between the corresponding AND and OR rows.

In present circuit designs, the AND array 10 followed by the OR array 12 is accomplished by using two OR arrays and inverter arrays. Therefore, an inverter array already exists between the AND and the OR (but not of the programmable type). This inverter array 14 can be modified to become an exclusive OR array without spending much extra silicon real estate and without sacrificing cycle time, since the number of total circuit levels contributing to the cycle time remains the same.

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