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Programmable Logic Array Error Detection and Error Correction

IP.com Disclosure Number: IPCOM000086098D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Logue, JC: AUTHOR [+2]

Abstract

By knowing the reliability problem and the failure mechanism of array circuitry 12, a failure detection (FD) circuit 10 can be built to detect the failure of a row (word line) or a column of the array 12.

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Programmable Logic Array Error Detection and Error Correction

By knowing the reliability problem and the failure mechanism of array circuitry 12, a failure detection (FD) circuit 10 can be built to detect the failure of a row (word line) or a column of the array 12.

The outputs of all the detection circuits are dot OR'ed together to indicate an AND array error or an OR array error. Assuming that the emitter-base of transistor 14 is shorted, the voltage at the base of transistor 10 (FD transistor) will be 0.7V (one diode voltage) higher than that of the normal condition and be able to turn on transistor 10' At normal condition (no emitter-base short), transistor 10 is off.

The threshold voltage of transistor 10 is controlled by the reference voltage (Vref) at the base of transistor 13. The outputs of all the detection circuits 10 are dot OR'ed together and fed to a sense amplifier 16. When any of the transistors 10 are on, there will be an error signal at the sensing amplifier output. The sensing amplifier 16 may or may not be needed depending on the array circuitry.

The system down time as well as the cost of engineering change will be minimized, if the error can be found and corrected electrically in the field within a short time. In order to achieve this; first, error detection and search circuits used to tell which row or which column has failed are required; second, a method of deleting the failed line is needed; and, finally, a few rows and columns having read/write memory cells have to be provided for replacing the deleted lines.

Fig. 2 shows the block diagram of the programmable logic array (PLA) error detection and correction scheme. The FD circuits 10 at the end of each row are similar to those shown in Fig. 1. The outputs of the FD circuits are scanned by the scanning counter 20. As the scanning counter de...