Browse Prior Art Database

Extended Translation Look Aside Buffer

IP.com Disclosure Number: IPCOM000086101D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Hogan, SG: AUTHOR [+2]

Abstract

Described is a method of simulating a 3-way or greater associative translation look-aside buffer (TLB).

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Extended Translation Look Aside Buffer

Described is a method of simulating a 3-way or greater associative translation look-aside buffer (TLB).

The primary TLB 10 works, as described in U.S. patent 3,829,840, to provide a real memory address when interrogated by a virtual address of which it retains a translation. When a translation is to be mapped out of TLB 10 it will be mapped into secondary TLB's 20 or 30 using a LRU (Least Recently Used) algorithm. When a "miss" occurs in the primary TLB 10, the secondary TLB's 20 or 30 will be checked for a "hit" before a new translation of the virtual address is requested.

If a hit occurs in the secondary TLB's the real address will be gated out and used with only a 2 machine cycle degradation. When a hit occurs in the secondary TLB, the selected translation will be moved to the primary TLB and the displaced primary translation will be put into the secondary TLB. This will insure that the most recently used translations will be in the primary TLB.

It should be noted that the TLB's 10, 20 and 30 do not have to be equal and can be selected to give the best cost/performance. It should also be noted that since the secondary TLB's 20 and 30 can be slower than the primary TLB 10, they can take advantage of slower and denser technologies. The larger the TLB's 20 and 30, the better the overall hit ratio.

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