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Browse Prior Art Database

Test Apparatus for Data Processing System

IP.com Disclosure Number: IPCOM000086103D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Bish, JJ: AUTHOR

Abstract

The apparatus of the drawing is connected to a host processor 2 on the left and to a device 3 that is to be tested on the right. A bus 4 carries parallel data from the host 3 and a bus 5 carries parallel data to the host. Similarly, serial data lines 6 and 7 carry data between the apparatus and the device 3 to be tested.

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Test Apparatus for Data Processing System

The apparatus of the drawing is connected to a host processor 2 on the left and to a device 3 that is to be tested on the right. A bus 4 carries parallel data from the host 3 and a bus 5 carries parallel data to the host. Similarly, serial data lines 6 and 7 carry data between the apparatus and the device 3 to be tested.

A scan register 8 can be loaded with data from the host 2 on line 4 in response to a host supplied control signal Set Scan Register on a line 9. When a latch 12 is set in response to a signal Scan In on line 13, an AND gate 14 transmits the contents of register 8 to the system under test on line 6.

A counter 15 can be loaded with a count value on bus 4 in response to a control signal Set Counter on a line 16. A timing shift register 17 receives the output of an oscillator 18, and it receives a start signal on a line 19 to produce pulses successively at its outputs 20 through 23. The signals on lines 20 and 21 are timing pulses that are supplied to the clock, not shown, of the system under test 3. The signal on line 22 steps counter 15 and the signal on line 23 steps register 8 to transfer a next bit to the system under test on line 6.

When counter 15 has been stepped to 0, a signal on line 26 resets latch 12 and ends the Scan In operation. Similarly, a latch 28 responds to a signal Scan Out on a line 29 to open AND gate 30 to transfer serial data on line 7 from the system under test 3 to register 8, for s...