Browse Prior Art Database

Overlapped Next Addressing in a Control System

IP.com Disclosure Number: IPCOM000086104D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Pedersen, RJ: AUTHOR

Abstract

Described is a design of a fully associative, high density, one-cycle access buffering system using random-access memory elements with access times approaching (or exceeding) the cycle time of the system.

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Overlapped Next Addressing in a Control System

Described is a design of a fully associative, high density, one-cycle access buffering system using random-access memory elements with access times approaching (or exceeding) the cycle time of the system.

Implementation of the directory portion of an associative buffering system changes as associativity changes. Small scale associativity (e.g., 2-way) usually permits a directory search to be done in parallel with the buffer access, while large scale associativity (fully associative) usually requires a serial directory search. As a result, a trade off of density and/or speed must be made to increase associativity. What follows is a scheme for bypassing the directory search for most buffer accesses, thereby eliminating or greatly reducing the degradation due to associativity.

The elements of the system necessary to this discussion are shown in Fig. 1. The application is a control storage buffering system where each control word in the Control Store Data Register 1 (CSDR) contains a Next Address (NA) field 2, which points to the word to be in control during the next cycle. The buffer 3 is fully associative on a line (group of control words with consecutive addresses) basis and, therefore, requires a directory 4 translation of these next addresses before they can be used as real addresses into the individual array elements. The Control Store Address Register 5 (CSAR) holds this translated address.

As shown in Fig. 1, the array address is made up of CSAR (0 to
r), and NA (m + 1 to n). Since CSAR is the directory translation of the line address NA (0 to m), it is a pointer to a line within the buffer 3. All address paths through the buffer 3 now begin directly at registers, and the serial directory search is eliminated.

Once CSAR has been set, subsequent accesses to the same line need not reference the directory.

What is needed is a mechanism to mask the additional time required to update CSAR when a branch is taken outside the line. A microorder is introduced as the means for overlapping the directory translation cycle with a cycle whose addressing need only be controlled by NA (m + 1 to n). A New Line microorder results in the alteration of the NA bit pattern of the word in which it is given.

The microword compiler replaces NA (0 to m) with the line address specified by the New Line order (this allows the control word width to remain constant). Upon encountering a New Line microorder, the hardware...