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Browse Prior Art Database

Associative Control Store System for Multiplication

IP.com Disclosure Number: IPCOM000086108D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Moore, JW: AUTHOR

Abstract

The drawing shows a representative portion of an associative store having an address section 2 and a data section 3. Input lines to the rows of section 2 carry a data word that is to be searched for in section 2. A search takes place along column positions, designated A through F, and a match signal occurs on an output line from a column that matches the inputs. A "?" in section 2 signifies that a position produces a match for either a 1 or a 0 bit at the row input, and with this feature a reduced number of entries can handle all possible combinations of inputs.

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Associative Control Store System for Multiplication

The drawing shows a representative portion of an associative store having an address section 2 and a data section 3. Input lines to the rows of section 2 carry a data word that is to be searched for in section 2. A search takes place along column positions, designated A through F, and a match signal occurs on an output line from a column that matches the inputs. A "?" in section 2 signifies that a position produces a match for either a 1 or a 0 bit at the row input, and with this feature a reduced number of entries can handle all possible combinations of inputs.

For some input data patterns, section 2 may produce multiple matches. When a particular column in section 2 is matched by the inputs, the corresponding column in section 3 is read to provide control signals on lines that are connected to the rows of store section 3. (The output data register of store section 3 is omitted in the drawing and lines connect each row to the component that it controls.)

The uppermost row in section 2 receives a signal Multiply from the op code portion of an instruction, and the other components in the drawing illustrate the general operation of this control store system in relation to a specific example of multiplying two numbers that are stored in registers 4 and 5. A two-bit counter 7 is incremented by one of the outputs of store section 3 through four count positions that represent four successive phases in the operation of the system. The example describes the instruction execution phase of the operation and it starts in the last step of a preceding phase with counter 7 in state 01, signifying that an instruction is being fetched. As a result of fetching and decoding this instruction, the value 1 appears on the line Multiply. In response to these row input signals to store section 2, a match occurs in column F and signals appear on the lines connected to the rows of store section 3 where a 1 bit appears in column F.

As the drawing shows, the following operations take place when the system is in this state. A status latch 8 is reset to 0. Counter 7 is incremented to a count value 10, and this count value is shown on the two counter outputs in the drawing. A gate is opened to set a value of 32...