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Three State Receiver Logical Circuit

IP.com Disclosure Number: IPCOM000086132D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Lindgren, CD: AUTHOR [+2]

Abstract

This logical circuit is responsive to three states of potential on a grounded two-conductor transmission line or bus arrangement, as determined by a three-state transmitter logical circuit arrangement.

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Three State Receiver Logical Circuit

This logical circuit is responsive to three states of potential on a grounded two-conductor transmission line or bus arrangement, as determined by a three- state transmitter logical circuit arrangement.

A transmission line is connected to input terminals 12,14 for applying zero or naught input in the form of a voltage at or close to ground, unit input in the form of a predetermined voltage away from ground as required by the circuit family involved, and a third state when the high impedance of the idling transmitter is presented to the input terminals 12,14.

Output terminals 16,18 and 20,22 will deliver zero voltage when the input terminals are at binary naught or zero voltage for transmitting binary naught (phi). These terminals will deliver a predetermined voltage indicating a binary unit when the input voltage is at the predetermined voltage for transmitting binary unit (1). Output terminals 24,26 are at zero voltage except when the transmitter is in the idle or high-impedance state, in which case the output terminals 16,18 are in the unit state but the terminals 20,22 are in the naughts state. Line A B C phi phi phi phi 1 1 1 phi HiZ 1 phi 1.

The circuitry is readily implemented in one semiconductor chip. The transistors are all of one type (NPN as shown) and only diodes and resistors are needed to complete the circuit. Inverting amplifiers and logical level setting circuitry isolated by coupling transistors are all that a...