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Sense Amplifier

IP.com Disclosure Number: IPCOM000086163D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Related People

Schuster, SE: AUTHOR

Abstract

Described is a sense amplifier which uses a nonlinear feedback path. The amplifier is self-compensating with regard to parameter and voltage variations. Clocking is simple and noncritical. Operation consists of closing a negative nonlinear feedback path to set the amplifier to its unity gain point. Once unity gain is reached the feedback path is broken and the amplifier operates in an open-ended fashion, where small changes around the unity gain point on the input are amplified and produce large changes at the output. The amplifier appears to be quite fast and suitable for memory sensing, digital/analog (D/A) comparators, level sensing on buses, etc.

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Sense Amplifier

Described is a sense amplifier which uses a nonlinear feedback path. The amplifier is self-compensating with regard to parameter and voltage variations. Clocking is simple and noncritical. Operation consists of closing a negative nonlinear feedback path to set the amplifier to its unity gain point. Once unity gain is reached the feedback path is broken and the amplifier operates in an open-ended fashion, where small changes around the unity gain point on the input are amplified and produce large changes at the output. The amplifier appears to be quite fast and suitable for memory sensing, digital/analog (D/A) comparators, level sensing on buses, etc.

A circuit diagram of the sense amplifier and associated circuitry required for memory sensing is shown in Fig. 1. Circuit operation will be described in this environment. The sequence of operation can be divided into the four time periods shown on Fig. 2. During an initialization period t(o), the bit sense line is charged to ~ V(r) through device 3. At the start of t(o) the bit sense line could either be low or high, depending on what was written/rewritten into the storage cell on the previous cycle.

The voltage on the bit sense line at the end of t(o) must be some amount greater than the maximum unity gain voltage of the amplifier (i.e., ~ V(r)). In fact V(r) could be replaced by V(dd) in which case the bit line would charge to ~ (V(dd) - V(t)). This change would slightly increase the time required in a subsequent part of the cycle to set the amplifier to its unity gain point. It should be noted that at the start of t(o) device 16 discharges node C so that device 11 is off. This prevents node A from discharging through devices 15, 14 & 11 during this precharge period.

The amplifier is set to its unity gain point by the nonlinear feedback during the t(1) portion of the cycle. Phi2 goes high at the beginning of t(1), turning the load devices of the amplifier on and turning device 16 off through devices 1 & 2. Since the voltage on node A is above the unity gain voltage, node D will go low. The output voltage is offset from the unity gain voltage by an amount equal to the offset from unity gain at the input times the gain of the amplifier. Therefore, device 11 is turned on hard and node D is quite low. Node A will start to discharge through devices 15, 14 & 11. The discharge will stop when the voltage between nodes F and D equals the threshold voltage of device 14.

The nonlinear feedback device 14 is crucial to this operation, since without it the amplifier will oscillate or overshoot the unity gain point. The discharge is fast since node D does not start to rise because of the amplifier gain until node A approaches the unity gain voltage. When device 14 turns off, the output voltage is a threshold voltage away from the unity gain voltage of the amplifier. However the input voltage is offset from the unity gain point by a very small amount delta V(1), equal to the thresho...