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Dynamic Memory Refresh System

IP.com Disclosure Number: IPCOM000086175D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Vrba, RA: AUTHOR

Abstract

The user of a dynamic memory generally faces a performance penalty because of the need to constantly refresh the charge on the internal data storage capacitors. On some memories this takes as much as 50% of the performance. Thus, given a 1.6 microsecond memory, a real memory cycle followed by a refresh cycle results in a 3.2 microsecond memory. The degraded performance of this memory will cause the user many problems and in some cases makes it unsuitable. An approach to simplify use of this type of memory is to use a refresh counter on-chip and appropriate data paths to gate it to the memory array. Therefore, it appears static to the user, but this approach still results in a 50% performance degradation.

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Dynamic Memory Refresh System

The user of a dynamic memory generally faces a performance penalty because of the need to constantly refresh the charge on the internal data storage capacitors. On some memories this takes as much as 50% of the performance. Thus, given a 1.6 microsecond memory, a real memory cycle followed by a refresh cycle results in a 3.2 microsecond memory. The degraded performance of this memory will cause the user many problems and in some cases makes it unsuitable. An approach to simplify use of this type of memory is to use a refresh counter on-chip and appropriate data paths to gate it to the memory array. Therefore, it appears static to the user, but this approach still results in a 50% performance degradation.

Described is a modification to alleviate this problem. This modification will double the memory performance for most users without costing slow users any logic for refresh overhead. Fig. 2 illustrates an overall system while Fig. 1 illustrates the details of a memory with this modification.

The purpose of a refresh cycle is to replace the charge that leaks off of the charge (data) storage capacitors. This is accomplished by a read cycle. A read cycle first destructively senses the data on each of the capacitors of a column, then amplifies it and stores a full charge back on each of the data storage capacitors in that column. A given memory will have N columns and M rows. Therefore, to refresh an entire NxM bits (or word) memory it must execute N refresh cycles addressing each of the N columns one by one.

It is the purpose of the refresh counter to step through these columns one by one. If a user could guarantee that access to all N columns could be accomplished within the required refresh time, then there would be no need to formally stop and refresh the memory. Additionally, a 1.6 microsecond memory or one that is twice as fast because the guaranteed refresh would be done incidental to an operation, would be the result.

Modification to a chip would consist of adding one stage to the refresh counter and bringing this stage's output (COMPLETE) off-chip, and adding an external reset to the refresh counter. A slow system would not use either of these signals, but would just toggle the refresh control line as currently specified. A fast system would time the refr...